diff -Nawur u-boot-1.1.2/board/xilinx/ml300/config.mk u-boot-1.1.2-virtex/board/xilinx/ml300/config.mk --- u-boot-1.1.2/board/xilinx/ml300/config.mk 2004-02-24 00:54:46.000000000 +0100 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/config.mk 2005-06-27 13:40:59.000000000 +0200 @@ -26,4 +26,4 @@ # #TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0x04000000 +TEXT_BASE = 0x00010000 diff -Nawur u-boot-1.1.2/board/xilinx/ml300/flash.c u-boot-1.1.2-virtex/board/xilinx/ml300/flash.c --- u-boot-1.1.2/board/xilinx/ml300/flash.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/flash.c 2005-07-08 09:16:38.000000000 +0200 @@ -0,0 +1,300 @@ +/* + * flash.c: Support code for the flash chips on the Xilinx ML2 board + * + * Copyright 2002 Mind NV + * + * http://www.mind.be/ + * + * Author : Peter De Schrijver (p2@mind.be) + * + * This software may be used and distributed according to the terms of + * the GNU General Public License (GPL) version 2, incorporated herein by + * reference. Drivers based on or derived from this code fall under the GPL + * and must retain the authorship, copyright and this license notice. This + * file is not a complete program and may only be used when the entire program + * is licensed under the GPL. + * + */ + +#include +#include +#include + +#define FLASH_BANK_SIZE (64*1024*1024) + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +#define SECT_SIZE (512*1024) + +#define CMD_READ_ARRAY 0x00FF00FF00FF00FULL +#define CMD_IDENTIFY 0x0090009000900090ULL +#define CMD_ERASE_SETUP 0x0020002000200020ULL +#define CMD_ERASE_CONFIRM 0x00D000D000D000D0ULL +#define CMD_PROGRAM 0x0040004000400040ULL +#define CMD_RESUME 0x00D000D000D000D0ULL +#define CMD_SUSPEND 0x00B000B000B000B0ULL +#define CMD_STATUS_READ 0x0070007000700070ULL +#define CMD_STATUS_RESET 0x0050005000500050ULL + +#define BIT_BUSY 0x0080008000800080ULL +#define BIT_ERASE_SUSPEND 0x004000400400040ULL +#define BIT_ERASE_ERROR 0x0020002000200020ULL +#define BIT_PROGRAM_ERROR 0x0010001000100010ULL +#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL +#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL +#define BIT_PROTECT_ERROR 0x0002000200020002ULL +#define BIT_UNDEFINED 0x0001000100010001ULL + +#define BIT_SEQUENCE_ERROR 0x0030003000300030ULL + +#define BIT_TIMEOUT 0x80000000 + + +inline void eieio(void) { + + __asm__ __volatile__ ("eieio" : : : "memory"); + +} + +ulong flash_init(void) { + + int i, j; + ulong size = 0; + + for(i=0;iflash_id & FLASH_VENDMASK) { + case (INTEL_MANUFACT & FLASH_VENDMASK): + printf("Intel: "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (INTEL_ID_28F128J3A & FLASH_TYPEMASK): + printf("4x 28F128J3A (128Mbit)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count); + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) + printf("\n "); + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); +} + +int flash_error (unsigned long long code) { + + if (code & BIT_TIMEOUT) { + printf ("Timeout\n"); + return ERR_TIMOUT; + } + + if (~code & BIT_BUSY) { + printf ("Busy\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_VPP_RANGE_ERROR) { + printf ("Vpp range error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_PROTECT_ERROR) { + printf ("Device protect error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_SEQUENCE_ERROR) { + printf ("Command seqence error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_ERASE_ERROR) { + printf ("Block erase error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_PROGRAM_ERROR) { + printf ("Program error\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_ERASE_SUSPEND) { + printf ("Block erase suspended\n"); + return ERR_PROG_ERROR; + } + + if (code & BIT_PROGRAM_SUSPEND) { + printf ("Program suspended\n"); + return ERR_PROG_ERROR; + } + + return ERR_OK; + +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) { + + int rc = ERR_OK; + int sect; + unsigned long long result; + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) + return ERR_INVAL; + + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) + return ERR_UNKNOWN_FLASH_VENDOR; + + for (sect=s_first; sect<=s_last; ++sect) + if (info->protect[sect]) + return ERR_PROTECTED; + + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { + volatile unsigned long long *addr= + (unsigned long long *)(info->start[sect]); + + printf("Erasing sector %2d ... ", sect); + + *addr=CMD_STATUS_RESET; + eieio(); + *addr=CMD_ERASE_SETUP; + eieio(); + *addr=CMD_ERASE_CONFIRM; + eieio(); + + do { + result = *addr; + } while(~result & BIT_BUSY); + + *addr=CMD_READ_ARRAY; + + if ((rc = flash_error(result)) == ERR_OK) + printf("ok.\n"); + else + break; + } + + if (ctrlc()) + printf("User Interrupt!\n"); + + return rc; +} + +volatile static int write_word (flash_info_t *info, ulong dest, unsigned long long data) { + + volatile unsigned long long *addr=(unsigned long long *)dest; + unsigned long long result; + int rc = ERR_OK; + + result=*addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + *addr=CMD_STATUS_RESET; + eieio(); + *addr=CMD_PROGRAM; + eieio(); + *addr=data; + eieio(); + + do { + result=*addr; + } while(~result & BIT_BUSY); + + *addr=CMD_READ_ARRAY; + + rc = flash_error(result); + + return rc; + +} + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) { + + ulong cp, wp; + unsigned long long data; + int l; + int i,rc; + + wp=(addr & ~7); + + if((l=addr-wp) != 0) { + data=0; + for(i=0,cp=wp;i> 8) | (*(uchar *)cp << 24); + + for (; i<8 && cnt>0; ++i) { + data = (data >> 8) | (*src++ << 24); + --cnt; + ++cp; + } + + for (; i<8; ++i, ++cp) + data = (data >> 8) | (*(uchar *)cp << 24); + + if ((rc = write_word(info, wp, data)) != 0) + return rc; + + wp+=8; + } + + while(cnt>=8) { + data=*((unsigned long long *)src); + if ((rc = write_word(info, wp, data)) != 0) + return rc; + src+=8; + wp+=8; + cnt-=8; + } + + if(cnt == 0) + return ERR_OK; + + data = 0; + for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) { + data = (data >> 8) | (*src++ << 24); + --cnt; + } + for (; i<8; ++i, ++cp) { + data = (data >> 8) | (*(uchar *)cp << 24); + } + + return write_word(info, wp, data); + +} diff -Nawur u-boot-1.1.2/board/xilinx/ml300/Makefile u-boot-1.1.2-virtex/board/xilinx/ml300/Makefile --- u-boot-1.1.2/board/xilinx/ml300/Makefile 2004-09-30 00:44:01.000000000 +0200 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/Makefile 2005-07-08 09:15:33.000000000 +0200 @@ -31,8 +31,7 @@ ../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \ ../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \ ../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \ - ../xilinx_enet/xemac_intr_dma.o ../xilinx_iic/iic_adapter.o \ - ../xilinx_iic/xiic_l.o ../common/xipif_v1_23_b.o \ + ../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \ ../common/xbasic_types.o ../common/xdma_channel.o \ ../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \ ../common/xversion.o \ diff -Nawur u-boot-1.1.2/board/xilinx/ml300/ml300.c u-boot-1.1.2-virtex/board/xilinx/ml300/ml300.c --- u-boot-1.1.2/board/xilinx/ml300/ml300.c 2004-09-30 00:44:01.000000000 +0200 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/ml300.c 2005-06-27 13:41:25.000000000 +0200 @@ -82,7 +82,7 @@ long int initdram(int board_type) { - return 128 * 1024 * 1024; + return 32 * 1024 * 1024; } int @@ -100,8 +100,8 @@ sysInfo->freqProcessor = XPAR_CORE_CLOCK_FREQ_HZ; /* only correct if the PLB and OPB run at the same frequency */ - sysInfo->freqPLB = XPAR_UARTNS550_0_CLOCK_FREQ_HZ; - sysInfo->freqPCI = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3; + sysInfo->freqPLB = 100000000;//XPAR_UARTNS550_0_CLOCK_FREQ_HZ; + sysInfo->freqPCI = 0;//XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 3; } ulong diff -Nawur u-boot-1.1.2/board/xilinx/ml300/serial.c u-boot-1.1.2-virtex/board/xilinx/ml300/serial.c --- u-boot-1.1.2/board/xilinx/ml300/serial.c 2004-02-24 00:54:46.000000000 +0100 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/serial.c 2005-06-27 13:42:43.000000000 +0200 @@ -1,155 +1,77 @@ /* - * Author: Xilinx, Inc. + * (C) Copyright 2004 Atmark Techno, Inc. * + * Yasushi SHOJI * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING - * ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx hardware products are not intended for use in life support - * appliances, devices, or systems. Use in such applications is - * expressly prohibited. - * - * - * (c) Copyright 2002-2004 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. + * See file CREDITS for list of people who contributed to this + * project. * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ -#include -#include -#include -#include -#include -#include "xparameters.h" +#include -#define USE_CHAN1 \ - ((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1)) -#define USE_CHAN2 \ - ((defined XPAR_UARTNS550_1_BASEADDR) && (defined CFG_INIT_CHAN2)) - -#if USE_CHAN1 -#include -#endif - -#if USE_CHAN1 -const NS16550_t COM_PORTS[] = { (NS16550_t) (XPAR_UARTNS550_0_BASEADDR + 3) -#if USE_CHAN2 - , (NS16550_t) (XPAR_UARTNS550_1_BASEADDR + 3) -#endif -}; -#endif - -int -serial_init(void) -{ -#if USE_CHAN1 - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor; - - clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; - (void) NS16550_init(COM_PORTS[0], clock_divisor); -#if USE_CHAN2 - clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; - (void) NS16550_init(COM_PORTS[1], clock_divisor); -#endif -#endif - return 0; +#ifdef CONFIG_XILINX_ML300 -} +#include "xparameters.h" +#include "xuartlite_l.h" -void -serial_putc(const char c) -{ - if (c == '\n') - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r'); +/* FIXME: we should convert these to in32 and out32 */ +#define IO_WORD(offset) (*(volatile unsigned long *)(offset)) +#define IO_SERIAL(offset) IO_WORD(CONFIG_SERIAL_BASE + (offset)) - NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c); -} +#define IO_SERIAL_RX_FIFO IO_SERIAL(XUL_RX_FIFO_OFFSET) +#define IO_SERIAL_TX_FIFO IO_SERIAL(XUL_TX_FIFO_OFFSET) +#define IO_SERIAL_STATUS IO_SERIAL(XUL_STATUS_REG_OFFSET) +#define IO_SERIAL_CONTROL IO_SERIAL(XUL_CONTROL_REG_OFFSET) -int -serial_getc(void) +int serial_init(void) { - return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]); + /* FIXME: Nothing for now. We should initialize fifo, etc */ + return 0; } -int -serial_tstc(void) +void serial_setbrg(void) { - return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]); + /* FIXME: what's this for? */ } -void -serial_setbrg(void) +void serial_putc(const char c) { -#if USE_CHAN1 - DECLARE_GLOBAL_DATA_PTR; - int clock_divisor; - - clock_divisor = XPAR_UARTNS550_0_CLOCK_FREQ_HZ / 16 / gd->baudrate; - NS16550_reinit(COM_PORTS[0], clock_divisor); -#if USE_CHAN2 - clock_divisor = XPAR_UARTNS550_1_CLOCK_FREQ_HZ / 16 / gd->baudrate; - NS16550_reinit(COM_PORTS[1], clock_divisor); -#endif -#endif + if (c == '\n') serial_putc('\r'); + while (IO_SERIAL_STATUS & XUL_SR_TX_FIFO_FULL); + IO_SERIAL_TX_FIFO = (unsigned char) (c & 0xff); } -void -serial_puts(const char *s) +void serial_puts(const char * s) { while (*s) { serial_putc(*s++); } } -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -void -kgdb_serial_init(void) -{ -} - -void -putDebugChar(int c) -{ - serial_putc(c); -} - -void -putDebugStr(const char *str) +int serial_getc(void) { - serial_puts(str); + while (!(IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA)); + return IO_SERIAL_RX_FIFO & 0xff; } -int -getDebugChar(void) +int serial_tstc(void) { - return serial_getc(); + return (IO_SERIAL_STATUS & XUL_SR_RX_FIFO_VALID_DATA); } -void -kgdb_interruptible(int yes) -{ - return; -} -#endif /* CFG_CMD_KGDB */ +#endif /* CONFIG_MICROBLZE */ diff -Nawur u-boot-1.1.2/board/xilinx/ml300/u-boot.lds u-boot-1.1.2-virtex/board/xilinx/ml300/u-boot.lds --- u-boot-1.1.2/board/xilinx/ml300/u-boot.lds 2004-02-24 00:54:46.000000000 +0100 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/u-boot.lds 2005-06-27 13:48:02.000000000 +0200 @@ -117,7 +117,7 @@ _edata = .; PROVIDE (edata = .); - __u_boot_cmd_start = .; + __u_boot_cmd_start = ADDR(.u_boot_cmd); .u_boot_cmd : { *(.u_boot_cmd) } __u_boot_cmd_end = .; diff -Nawur u-boot-1.1.2/board/xilinx/ml300/xparameters.h u-boot-1.1.2-virtex/board/xilinx/ml300/xparameters.h --- u-boot-1.1.2/board/xilinx/ml300/xparameters.h 2004-09-30 00:44:01.000000000 +0200 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/xparameters.h 2005-06-29 16:10:25.000000000 +0200 @@ -1,196 +1,84 @@ + /******************************************************************* * * CAUTION: This file is automatically generated by libgen. -* Version: Xilinx EDK 6.2 EDK_Gm.11 +* Version: Xilinx EDK 7.1 EDK_H.10.4 * DO NOT EDIT. * -* Copyright (c) 2003 Xilinx, Inc. All rights reserved. +* Copyright (c) 2005 Xilinx, Inc. All rights reserved. * * Description: Driver parameters * *******************************************************************/ -/******************************************************************/ - -/* U-Boot Redefines */ - -/******************************************************************/ - -#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000) -#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR -#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID -#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000) -#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR -#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ -#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID - -/******************************************************************/ - -#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR -#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR -#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR -#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR -#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR -#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT -#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST -#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST -#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID - -/******************************************************************/ - -#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ - -/******************************************************************/ - -#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400 -#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF -#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0 - -/******************************************************************/ - -#define XPAR_XPCI_NUM_INSTANCES 1 -#define XPAR_XPCI_CLOCK_HZ 33333333 -#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0 -#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF -#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000 -#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004 -#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000 -#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000 -#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF -#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000 -#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF +#define STDIN_BASEADDRESS 0x80600000 +#define STDOUT_BASEADDRESS 0x80600000 /******************************************************************/ #define XPAR_XEMAC_NUM_INSTANCES 1 -#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000 -#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF -#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0 -#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1 -#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1 -#define XPAR_OPB_ETHERNET_0_MII_EXIST 1 +#define XPAR_ETHERNET_MAC_BASEADDR 0x80C00000 +#define XPAR_ETHERNET_MAC_HIGHADDR 0x80C0FFFF +#define XPAR_ETHERNET_MAC_DEVICE_ID 0 +#define XPAR_ETHERNET_MAC_ERR_COUNT_EXIST 1 +#define XPAR_ETHERNET_MAC_DMA_PRESENT 1 +#define XPAR_ETHERNET_MAC_MII_EXIST 1 +#define XPAR_ETHERNET_MAC_CAM_EXIST 0 +#define XPAR_ETHERNET_MAC_JUMBO_EXIST 0 /******************************************************************/ -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000 -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7) -#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1 -#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8) -#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F) -#define XPAR_XGPIO_NUM_INSTANCES 2 - -/******************************************************************/ - -#define XPAR_XIIC_NUM_INSTANCES 1 -#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000 -#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF -#define XPAR_OPB_IIC_0_DEVICE_ID 0 -#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0 - -/******************************************************************/ - -#define XPAR_XUARTNS550_NUM_INSTANCES 2 -#define XPAR_XUARTNS550_CLOCK_HZ 100000000 -#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000 -#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF -#define XPAR_OPB_UART16550_0_DEVICE_ID 0 -#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000 -#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF -#define XPAR_OPB_UART16550_1_DEVICE_ID 1 - -/******************************************************************/ - -#define XPAR_XSPI_NUM_INSTANCES 1 -#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000 -#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F -#define XPAR_OPB_SPI_0_DEVICE_ID 0 -#define XPAR_OPB_SPI_0_FIFO_EXIST 1 -#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0 -#define XPAR_OPB_SPI_0_NUM_SS_BITS 1 - -/******************************************************************/ - -#define XPAR_XPS2_NUM_INSTANCES 2 -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000 -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F) -#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1 -#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000) -#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F) - -/******************************************************************/ - -#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1 -#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000 -#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007 -#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0 - -/******************************************************************/ - -#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000 -#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF -#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000 -#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF -#define XPAR_PLB_DDR_0_BASEADDR 0x00000000 -#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF +#define XPAR_XUARTLITE_NUM_INSTANCES 1 +#define XPAR_RS232_BASEADDR 0x80600000 +#define XPAR_RS232_HIGHADDR 0x8060FFFF +#define XPAR_RS232_DEVICE_ID 0 +#define XPAR_RS232_BAUDRATE 115200 +#define XPAR_RS232_USE_PARITY 0 +#define XPAR_RS232_ODD_PARITY 0 +#define XPAR_RS232_DATA_BITS 8 /******************************************************************/ +#define XPAR_INTC_MAX_NUM_INTR_INPUTS 1 #define XPAR_XINTC_HAS_IPR 1 -#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18 #define XPAR_XINTC_USE_DCR 0 #define XPAR_XINTC_NUM_INSTANCES 1 -#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0 -#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF -#define XPAR_DCR_INTC_0_DEVICE_ID 0 -#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000 +#define XPAR_OPB_INTC_0_BASEADDR 0x81200000 +#define XPAR_OPB_INTC_0_HIGHADDR 0x8120FFFF +#define XPAR_OPB_INTC_0_DEVICE_ID 0 +#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000001 /******************************************************************/ -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0 -#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2 -#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3 -#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4 -#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5 -#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6 -#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8 -#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9 -#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10 -#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12 -#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13 -#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14 -#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15 -#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16 -#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17 +#define XPAR_INTC_SINGLE_BASEADDR 0x81200000 +#define XPAR_INTC_SINGLE_HIGHADDR 0x8120FFFF +#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#define XPAR_RS232_INTERRUPT_MASK 0X000001 +#define XPAR_OPB_INTC_0_RS232_INTERRUPT_INTR 0 /******************************************************************/ -#define XPAR_XTFT_NUM_INSTANCES 1 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200 -#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207 -#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0 +#define XPAR_SDRAM_64MX16_BASEADDR 0x00000000 +#define XPAR_SDRAM_64MX16_HIGHADDR 0x01FFFFFF /******************************************************************/ -#define XPAR_XSYSACE_MEM_WIDTH 8 -#define XPAR_XSYSACE_NUM_INSTANCES 1 -#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000 -#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF -#define XPAR_OPB_SYSACE_0_DEVICE_ID 0 -#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8 +#define XPAR_PLB_BRAM_IF_CNTLR_1_BASEADDR 0xffff0000 +#define XPAR_PLB_BRAM_IF_CNTLR_1_HIGHADDR 0xffffffff /******************************************************************/ -#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000 +#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 100000000 /******************************************************************/ + +#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ +#define CONFIG_SERIAL_BASE XPAR_RS232_BASEADDR + + +#define XPAR_EMAC_0_DEVICE_ID XPAR_ETHERNET_MAC_DEVICE_ID +#define XPAR_OPB_ETHERNET_0_DEVICE_ID XPAR_ETHERNET_MAC_DEVICE_ID +#define XPAR_OPB_ETHERNET_0_BASEADDR XPAR_ETHERNET_MAC_BASEADDR +#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST XPAR_ETHERNET_MAC_ERR_COUNT_EXIST +#define XPAR_OPB_ETHERNET_0_DMA_PRESENT XPAR_ETHERNET_MAC_DMA_PRESENT +#define XPAR_OPB_ETHERNET_0_MII_EXIST XPAR_ETHERNET_MAC_MII_EXIST diff -Nawur u-boot-1.1.2/board/xilinx/ml300/xuartlite_l.h u-boot-1.1.2-virtex/board/xilinx/ml300/xuartlite_l.h --- u-boot-1.1.2/board/xilinx/ml300/xuartlite_l.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-1.1.2-virtex/board/xilinx/ml300/xuartlite_l.h 2005-06-27 13:42:27.000000000 +0200 @@ -0,0 +1,256 @@ +/***************************************************************************** +* +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" +* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND +* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, +* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, +* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION +* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE. +* +* (c) Copyright 2002 Xilinx Inc. +* All rights reserved. +* +*****************************************************************************/ +/****************************************************************************/ +/** +* +* @file xuartlite_l.h +* +* This header file contains identifiers and low-level driver functions (or +* macros) that can be used to access the device. High-level driver functions +* are defined in xuartlite.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b rpm  04/25/02 First release
+*
+* +*****************************************************************************/ + +#ifndef XUARTLITE_L_H /* prevent circular inclusions */ +#define XUARTLITE_L_H /* by using protection macros */ + +/***************************** Include Files ********************************/ + +#include "xbasic_types.h" +#include "xio.h" + +/************************** Constant Definitions ****************************/ + +/* UART Lite register offsets */ + +#define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ +#define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ +#define XUL_STATUS_REG_OFFSET 8 /* status register, read only */ +#define XUL_CONTROL_REG_OFFSET 12 /* control register, write only */ + +/* control register bit positions */ + +#define XUL_CR_ENABLE_INTR 0x10 /* enable interrupt */ +#define XUL_CR_FIFO_RX_RESET 0x02 /* reset receive FIFO */ +#define XUL_CR_FIFO_TX_RESET 0x01 /* reset transmit FIFO */ + +/* status register bit positions */ + +#define XUL_SR_PARITY_ERROR 0x80 +#define XUL_SR_FRAMING_ERROR 0x40 +#define XUL_SR_OVERRUN_ERROR 0x20 +#define XUL_SR_INTR_ENABLED 0x10 /* interrupt enabled */ +#define XUL_SR_TX_FIFO_FULL 0x08 /* transmit FIFO full */ +#define XUL_SR_TX_FIFO_EMPTY 0x04 /* transmit FIFO empty */ +#define XUL_SR_RX_FIFO_FULL 0x02 /* receive FIFO full */ +#define XUL_SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */ + +/* the following constant specifies the size of the FIFOs, the size of the + * FIFOs includes the transmitter and receiver such that it is the total number + * of bytes that the UART can buffer + */ +#define XUL_FIFO_SIZE 16 + +/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a + * per instance basis + */ +#define XUL_STOP_BITS 1 + +/* Parity definitions + */ +#define XUL_PARITY_NONE 0 +#define XUL_PARITY_ODD 1 +#define XUL_PARITY_EVEN 2 + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/***************************************************************************** +* +* Low-level driver macros and functions. The list below provides signatures +* to help the user use the macros. +* +* void XUartLite_mSetControlReg(u32 BaseAddress, u32 Mask) +* u32 XUartLite_mGetControlReg(u32 BaseAddress) +* u32 XUartLite_mGetStatusReg(u32 BaseAddress) +* +* Xboolean XUartLite_mIsReceiveEmpty(u32 BaseAddress) +* Xboolean XUartLite_mIsTransmitFull(u32 BaseAddress) +* Xboolean XUartLite_mIsIntrEnabled(u32 BaseAddress) +* +* void XUartLite_mEnableIntr(u32 BaseAddress) +* void XUartLite_mDisableIntr(u32 BaseAddress) +* +* void XUartLite_SendByte(u32 BaseAddress, u8 Data); +* u8 XUartLite_RecvByte(u32 BaseAddress); +* +*****************************************************************************/ + +/****************************************************************************/ +/** +* +* Set the contents of the control register. Use the XUL_CR_* constants defined +* above to create the bit-mask to be written to the register. +* +* @param BaseAddress is the base address of the device +* @param Mask is the 32-bit value to write to the control register +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mSetControlReg(BaseAddress, Mask) \ + XIo_Out32((BaseAddress) + XUL_CONTROL_REG_OFFSET, (Mask)) + + +/****************************************************************************/ +/** +* +* Get the contents of the control register. Use the XUL_CR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the control register. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mGetControlReg(BaseAddress) \ + XIo_In32((BaseAddress) + XUL_CONTROL_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Get the contents of the status register. Use the XUL_SR_* constants defined +* above to interpret the bit-mask returned. +* +* @param BaseAddress is the base address of the device +* +* @return A 32-bit value representing the contents of the status register. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mGetStatusReg(BaseAddress) \ + XIo_In32((BaseAddress) + XUL_STATUS_REG_OFFSET) + + +/****************************************************************************/ +/** +* +* Check to see if the receiver has data. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the receiver is empty, XFALSE if there is data present. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsReceiveEmpty(BaseAddress) \ + (!(XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA)) + + +/****************************************************************************/ +/** +* +* Check to see if the transmitter is full. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the transmitter is full, XFALSE otherwise. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsTransmitFull(BaseAddress) \ + (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) + + +/****************************************************************************/ +/** +* +* Check to see if the interrupt is enabled. +* +* @param BaseAddress is the base address of the device +* +* @return XTRUE if the interrupt is enabled, XFALSE otherwise. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mIsIntrEnabled(BaseAddress) \ + (XUartLite_mGetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) + + +/****************************************************************************/ +/** +* +* Enable the device interrupt. Preserve the contents of the control register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mEnableIntr(BaseAddress) \ + XUartLite_mSetControlReg((BaseAddress), \ + XUartLite_mGetControlReg((BaseAddress)) | XUL_CR_ENABLE_INTR) + + +/****************************************************************************/ +/** +* +* Disable the device interrupt. Preserve the contents of the control register. +* +* @param BaseAddress is the base address of the device +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XUartLite_mDisableIntr(BaseAddress) \ + XUartLite_mSetControlReg((BaseAddress), \ + XUartLite_mGetControlReg((BaseAddress)) & ~XUL_CR_ENABLE_INTR) + + +/************************** Function Prototypes *****************************/ + +void XUartLite_SendByte(u32 BaseAddress, u8 Data); +u8 XUartLite_RecvByte(u32 BaseAddress); + + +#endif /* end of protection macro */ diff -Nawur u-boot-1.1.2/common/cmd_ace.c u-boot-1.1.2-virtex/common/cmd_ace.c --- u-boot-1.1.2/common/cmd_ace.c 2004-09-30 00:55:14.000000000 +0200 +++ u-boot-1.1.2-virtex/common/cmd_ace.c 2005-07-08 09:12:01.000000000 +0200 @@ -127,6 +127,8 @@ systemace_dev.blksz = 512; systemace_dev.removable = 1; systemace_dev.block_read = systemace_read; + + init_part(&systemace_dev); } return &systemace_dev; diff -Nawur u-boot-1.1.2/cpu/ppc4xx/start.S u-boot-1.1.2-virtex/cpu/ppc4xx/start.S --- u-boot-1.1.2/cpu/ppc4xx/start.S 2004-02-07 00:19:52.000000000 +0100 +++ u-boot-1.1.2-virtex/cpu/ppc4xx/start.S 2005-07-06 14:59:14.000000000 +0200 @@ -340,23 +340,6 @@ mtspr tcr,r0 /* disable all */ mtspr esr,r0 /* clear exception syndrome register */ mtxer r0 /* clear integer exception register */ -#if !defined(CONFIG_440_GX) - lis r1,0x0002 /* set CE bit (Critical Exceptions) */ - ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */ - mtmsr r1 /* change MSR */ -#else - bl __440gx_msr_set - b __440gx_msr_continue - -__440gx_msr_set: - lis r1, 0x0002 /* set CE bit (Critical Exceptions) */ - ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */ - mtspr srr1,r1 - mflr r1 - mtspr srr0,r1 - rfi -__440gx_msr_continue: -#endif /*----------------------------------------------------------------*/ /* Debug setup -- some (not very good) ice's need an event*/ @@ -439,9 +422,6 @@ mtspr esr,r0 /* clear Exception Syndrome Reg */ mttcr r0 /* timer control register */ mtexier r0 /* disable all interrupts */ - addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */ - oris r4,r4,0x2 /* set CE bit (Critical Exceptions) */ - mtmsr r4 /* change MSR */ addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */ ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */ mtdbsr r4 /* clear/reset the dbsr */ @@ -552,9 +532,6 @@ mttcr r4 /* clear Timer Control Reg */ mtxer r4 /* clear Fixed-Point Exception Reg */ mtevpr r4 /* clear Exception Vector Prefix Reg */ - addi r4,r0,0x1000 /* set ME bit (Machine Exceptions) */ - oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */ - mtmsr r4 /* change MSR */ addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ /* dbsr is cleared by setting bits to 1) */ mtdbsr r4 /* clear/reset the dbsr */ @@ -1409,6 +1386,24 @@ cmplw 0, r7, r8 blt 4b +#if !defined(CONFIG_440_GX) + addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ + oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ + mtmsr r7 /* change MSR */ +#else + bl __440gx_msr_set + b __440gx_msr_continue + +__440gx_msr_set: + addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ + oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ + mtspr srr1,r7 + mflr r7 + mtspr srr0,r7 + rfi +__440gx_msr_continue: +#endif + mtlr r4 /* restore link register */ blr diff -Nawur u-boot-1.1.2/doc/README.ml300 u-boot-1.1.2-virtex/doc/README.ml300 --- u-boot-1.1.2/doc/README.ml300 2004-02-24 00:54:51.000000000 +0100 +++ u-boot-1.1.2-virtex/doc/README.ml300 2005-07-06 15:15:22.000000000 +0200 @@ -126,3 +126,8 @@ EDK: http://www.xilinx.com/edk ISE: http://www.xilinx.com/ise Reference Design: http://www.xilinx.com/ise/embedded/edk_examples.htm + +6. Warning +---------- + +It was reported XMD make a spurious "Machine Check Exception". diff -Nawur u-boot-1.1.2/include/configs/ml300.h u-boot-1.1.2-virtex/include/configs/ml300.h --- u-boot-1.1.2/include/configs/ml300.h 2004-12-31 10:32:54.000000000 +0100 +++ u-boot-1.1.2-virtex/include/configs/ml300.h 2005-07-08 09:14:30.000000000 +0200 @@ -1,171 +1,71 @@ -/* - * ML300.h: ML300 specific config options - * - * http://www.xilinx.com/ml300 - * - * Derived from : ML2.h - * - * Author: Xilinx, Inc. - * - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * - * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A - * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, - * XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE - * FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR - * OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. - * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO - * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY - * WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM - * CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND - * FITNESS FOR A PARTICULAR PURPOSE. - * - * - * Xilinx products are not intended for use in life support appliances, - * devices, or systems. Use in such applications is expressly prohibited. - * - * - * (c) Copyright 2002 Xilinx Inc. - * All rights reserved. - * - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* #define DEBUG */ -/* #define ET_DEBUG 1 */ - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_405 1 /* This is a PPC405 CPU */ -#define CONFIG_4xx 1 /* ...member of PPC4xx family */ -#define CONFIG_XILINX_ML300 1 /* ...on a Xilinx ML300 board */ +#define CONFIG_405 +#define CONFIG_XILINX_ML300 -#define CONFIG_SYSTEMACE 1 -#define CONFIG_DOS_PARTITION 1 -#define CFG_SYSTEMACE_BASE XPAR_OPB_SYSACE_0_BASEADDR -#define CFG_SYSTEMACE_WIDTH XPAR_XSYSACE_MEM_WIDTH - -#define CFG_ENV_IS_IN_EEPROM 1 /* environment is in EEPROM */ - -/* following are used only if env is in EEPROM */ -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_I2C_EEPROM_ADDR XPAR_PERSISTENT_0_IIC_0_EEPROMADDR -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_ENV_OFFSET XPAR_PERSISTENT_0_IIC_0_BASEADDR -#define CONFIG_MISC_INIT_R 1 /* used to call out convert_env() */ -#define CONFIG_ENV_OVERWRITE 1 /* allow users to update ethaddr and serial# */ -#endif - -#include "../board/xilinx/ml300/xparameters.h" - -#define CFG_NO_FLASH 1 /* no flash */ -#define CFG_ENV_SIZE XPAR_PERSISTENT_0_IIC_0_HIGHADDR - XPAR_PERSISTENT_0_IIC_0_BASEADDR + 1 -#define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ - -#define CONFIG_BOOTARGS "console=ttyS0,9600 ip=off " \ - "root=/dev/xsysace/disc0/part3 rw" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \ - CFG_CMD_IMLS ) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \ - & ~REMOVE_COMMANDS) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NVRAM +#define CFG_ENV_SIZE 1024 +#define CFG_ENV_ADDR 0xFFFF0000 -/* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ -/* 300000000 */ +#define CFG_INIT_RAM_ADDR 0x00000000 +#define CFG_INIT_RAM_END 0x0000FFFF -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ - -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ - -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CFG_DUART_CHAN 0 -#define CFG_NS16550_REG_SIZE -4 -#define CFG_NS16550 1 -#define CFG_INIT_CHAN1 1 - -/* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ - -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 - */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MONITOR_BASE 0x04000000 -#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CFG_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CFG_MONITOR_BASE 0x00010000 +#define CFG_MONITOR_LEN (256 * 1024) +#define CFG_MALLOC_LEN (128 * 1024) + +#define CFG_SDRAM_BASE 0x00000000 // doit absolument être à 0 + +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL| CFG_CMD_FAT) & ~CFG_CMD_IMLS & ~CFG_CMD_FLASH) +#include +#undef CFG_CMD_SETGETDCR + +#define CFG_MEMTEST_START 0x00800000 +#define CFG_MEMTEST_END 0x00A00000 + +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 + +#define CFG_BAUDRATE_TABLE {19200} +#define CONFIG_BAUDRATE 19200 + +#define CFG_BARGSIZE CFG_CBSIZE +#define CFG_BOOTMAPSZ (8 << 20) +#define CFG_LOAD_ADDR 0x00800000 + +#define CONFIG_LOADS_ECHO 1 +#define CFG_LONGHELP +#define CFG_PROMPT "uboot# " +#define CFG_CBSIZE 256 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 +#define CFG_BARGSIZE CFG_CBSIZE +#define CFG_EXTBDINFO +#define CFG_HZ 1000 + +#define CONFIG_SYSTEMACE 1 +#define CFG_SYSTEMACE_BASE 0x81800000 +#define CFG_SYSTEMACE_WIDTH 8 +#define CONFIG_DOS_PARTITION + +#define CONFIG_ETHADDR 0x00:0x0a:0x35:0x00:0x22:0x01 +#define CONFIG_IPADDR 192.168.1.133 +#define CONFIG_SERVERIP 192.168.1.132 +//marche pas : #define CFG_TFTP_LOADADDR 0x00400000 +#define CONFIG_EXTRA_ENV_SETTINGS "loadaddr=0x00800000\0" \ + "bootfile=uImage\0" \ + "" + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTCOMMAND "tftp 0x800000 uImage; tftp 0x900000 uRamdisk; bootm 0x800000 0x900000" + +#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/ram0" + +#define CONFIG_USE_XMD + +#define DEBUG + -#endif /* __CONFIG_H */